View 74LCX74M_202550.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74LCX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS
s s
s
s
s s
s
s
s
s
5V TOLERANT INPUTS HIGH SPEED : fMAX = 150 MHz (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74LCX74M T&R 74LCX74MTR 74LCX74TTR
DESCRIPTION The 74LCX74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. PIN CONNECTION AND IEC LOGIC SYMBOLS
A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
September 2001
1/11
74LCX74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset - Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS CLR L H L H H H
X : Don't Care
OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET
PR H L L H H H
2/11
74LCX74
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol V CC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (V CC = 0V) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 50 - 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO VO IOH, IOL IOH, IOL Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage (V CC = 0V) Output Voltage (High or Low State) High or Low Level Output Current (V CC = 3.0 to 3.6V) High or Low Level Output Current (V CC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) Parameter Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -55 to 125 0 to 10 Unit V V V V mA mA C ns/V
1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V
3/11
74LCX74
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) -40 to 85 C Min. 2.0 2.7 to 3.6 0.8 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 II Ioff ICC ICC Input Leakage Current Power Off Leakage Current Quiescent Supply Current ICC incr. per Input 2.7 to 3.6 0 2.7 to 3.6 2.7 to 3.6 I O=-100 A IO=-12 mA IO=-18 mA IO=-24 mA IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5V V I or VO = 5.5V VI = VCC or GND VI or VO= 3.6 to 5.5V VIH = VCC - 0.6V VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 10 10 500 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 10 10 500 A A A A V V 0.8 V Max. Value -55 to 125 C Min. 2.0 Max. V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 CL = 50pF VIL = 0V, V IH = 3.3V Value TA = 25 C Min. Typ. 0.8 -0.8 Max. V Unit
VOLP V OLV
Dynamic Low Level Quiet Output (note 1)
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
4/11
74LCX74
AC ELECTRICAL CHARACTERISTICS
Test Conditi on Symbol Parameter VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 CL (pF) 50 50 50 50 RL () 500 500 500 500 ts = t r (ns) 2.5 2.5 2.5 2.5 -40 to 85 C Min. 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 3.0 3.0 0 0 150 1.0 Max. 8.0 7.0 8.0 7.0 Value -55 to 125 C Min. 1.5 1.5 1.5 1.5 3.5 3.5 1.5 1.5 4.0 4.0 0 0 150 1.0 Max. 9.2 8.0 9.2 8.0 ns ns ns ns Unit
tPLH tPHL tPLH tPHL
Propagation Delay Time (CK to Q or Q) Propagation Delay Time (PR or CLR to Q or Q) Setup Time, HIGH or LOW level D to CK Hold Time, HIGH or LOW level D to CK CK Pulse Width, HIGH or LOW PR or CLR Pulse Width, LOW Recovery Time PR or CLR to CK Clock Pulse Frequency Output To Output Skew Time (note1, 2)
tS th tW
50
500
2.5
ns
trec fMAX tOSLH tOSHL
50 50 50
500 500 500
2.5 2.5 2.5
ns MHz ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 VIN = 0 to VCC fIN = 10MHz V IN = 0 or VCC Value TA = 25 C Min. Typ. 6 40 Max. pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per Fli p-Flop)
5/11
74LCX74
TEST CIRCUIT
C L = 50 pF or equivalent (includes jig and probe capacitance) R L = 500 or equivalent R T = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/11
74LCX74
WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
7/11
74LCX74
WAVEFORM 3 : RECOVERY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 4 : PULSE WIDTH (f=1MHz; 50% duty cycle)
8/11
74LCX74
SO-14 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13G
9/11
74LCX74
TSSOP14 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
10/11
74LCX74
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com
11/11

▲Up To Search▲

Price & Availability of 74LCX74M

	To Download 74LCX74M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .